AI tools: Why Software Sprints While Chip Design Walks

A hype-cycle analysis across two engineering disciplines

Every technology goes through the same arc. Initial excitement inflates expectations beyond what the technology can deliver. Reality sets in. The technology falls into a trough of disillusionment. Then, slowly, the teams that stayed the course figure out what actually works — and the technology climbs toward genuine, lasting productivity.

This is the Gartner Hype Cycle — a framework the semiconductor industry has been curiously slow to apply to itself. Over the past few weeks I’ve done exactly that: first for AI in chip design, then for AI in software development. The two pictures look very different. And that difference is worth understanding.

Below are both analyses, followed by a deeper look at why the gap exists — and what the chip design industry needs to do about it.

Part 1: AI in Chip Design

The Hype Cycle for EDA and Semiconductor Design

This year's DVCon U.S. conference, which took place last week, set up its central panel theme as "𝗜𝘀 𝗔𝗜 𝘁𝗵𝗲 𝗞𝗲𝘆 𝘁𝗼 𝗘𝗻𝗱𝗶𝗻𝗴 𝘁𝗵𝗲 𝗩𝗲𝗿𝗶𝗳𝗶𝗰𝗮𝘁𝗶𝗼𝗻 𝗕𝗼𝘁𝘁𝗹𝗲𝗻𝗲𝗰𝗸?"
The panel's official page said it would "debate whether AI is truly the key to ending the verification bottleneck — or just the next over-hyped technology."
That phrase — 𝘰𝘷𝘦𝘳-𝘩𝘺𝘱𝘦𝘥 𝘵𝘦𝘤𝘩𝘯𝘰𝘭𝘰𝘨𝘺 — made me want to apply a well-known framework: the 𝗚𝗮𝗿𝘁𝗻𝗲𝗿 𝗛𝘆𝗽𝗲 𝗖𝘆𝗰𝗹𝗲. (If you're unfamiliar with the model, check here for explanation)

So where does AI in chip design actually sit?
As is typical across many technological segments, different use cases are in different stages of the cycle. Placement says nothing about a use case’s potential — only about the current state of affairs:

• Slope of Enlightenment — AI-assisted code generation and copilots. Past the hype and quietly delivering real, bounded value in daily workflows. Python scripts, small design blocks, controlled RTL modifications. Human in the loop — but that’s fine, because it’s actually working.

• Early Slope — AI-assisted debugging and coverage triage. Showing credible results in controlled environments, with early production deployments underway. The trajectory is promising.

• Peak / Entering Trough — LLM-based full RTL generation. Heavy vendor enthusiasm, but still limited large-scale real-world results. A significant gap between demo and production reality.

• Peak — Agentic EDA. Autonomous systems that design and verify chips with minimal human intervention. The vision is compelling, but production reality isn’t there yet.

• Innovation Trigger — Circuit Foundation Models. Multimodal models that natively understand RTL, netlists, and physical layouts simultaneously. The foundational technology that could change everything — when it arrives.

Figure 1: AI in Chip Design — Hype Cycle placement as of March 2026

This is not a reason for pessimism. It’s a reason for precision. The companies that win in AI-assisted chip design won’t be the ones deploying the most AI tools. They’ll be the ones who are honest about which capabilities are on the Slope today — and build on those — while investing patiently in the infrastructure needed to climb the harder problems.

Part 2: AI in Software Development

A Different Hype Cycle — A More Advanced One

After I posted about chip design on Linkedin, several people asked what the equivalent picture looks like for software development. I’m not an expert in software — chip design is my home turf — but here’s my best read:

• Plateau of Productivity — IDE Copilots & Basic Chat. GitHub Copilot, Cursor, and similar tools are mature, stable, and used daily. Copilot alone has surpassed 20 million users and is deployed by 90% of Fortune 100 companies. This conversation is over. It’s just how software engineers work now.

• Slope of Enlightenment — Persistent Memory & Reliable Agent Loops. The teams climbing out of the trough aren’t waiting for better models — they’re building better guardrails. Checkpoints, prompt libraries, deterministic “beats” to keep agents on track and prevent the “Ralph Wiggum Loop” — where an agent retries the same failing step endlessly without realizing it’s stuck.

• Trough of Disillusionment — “Doom Loops” & High Costs. Anyone who has tried to hand a complex task to an agent knows this place. Spiraling errors, frontier model bills, and nothing to show for it. (The trough isn’t a tool. It’s an experience.)

• Peak of Inflated Expectations — “Out-the-Loop” Agentic Coding. Hand off a full work package, receive a completed artifact. Compelling but not quite real at scale yet.

• Innovation Trigger — Multi-Agent Orchestration. Fleets of specialized sub-agents tackling complex problems together. The vision is powerful. The production patterns are still being written.

Figure 2: AI in Software Development — Hype Cycle placement as of March 2026

Part 3: Why the Gap Exists

The Structural Reasons Software AI Runs Ahead

Look at the two hype cycles side by side and the gap is striking at every stage, not just one.

In software, IDE copilots are at the Plateau of Productivity — the conversation is over, it’s infrastructure. In chip design, the equivalent sits on the Slope of Enlightenment, still earning its credibility. In software, agentic coding is at the Peak — the dominant topic at every developer conference. In chip design, Agentic EDA is also at the Peak, but with one critical difference: the software community is already living through the disillusionment of that peak, actively coining terms like “doom loops,” “Ralph Wiggum Loop,” and “out-of-loop coding” to describe the failure modes they’re encountering and solving. Chip design hasn’t even reached that stage of productive disillusionment yet.

The fact that software has a specialized vocabulary for agentic failure modes — and chip design doesn’t — is itself a measure of the gap. You only name failure modes you’ve experienced at scale.

The reasons are structural, rooted in four fundamental differences between the two domains. Each is an independent explanation for the lag; together, they compound.

1. The Training Data Problem

GitHub now hosts over 518 million repositories. Billions of lines of open-source Python, JavaScript, Java, and C++ have been publicly available for decades — enough to train models that genuinely understand software patterns at scale. Python alone had 2.6 million active contributors in 2025, growing 48% year-over-year.

RTL is almost entirely proprietary. The HDL code inside a chip design never leaves the company that wrote it. There is no public corpus of Verilog comparable to what exists for software. Verilog and SystemVerilog combined account for fewer than 7,000 publicly tagged repositories on GitHub — against 518 million total. A model trained on chip design data is working with a fundamentally different order of magnitude than one trained on software. And the public numbers almost certainly understate the real gap: most production RTL never reaches GitHub in the first place. The training data problem is even worse than the numbers suggest.

2. The Feedback Loop Problem

When a software AI generates code, you know within seconds whether it works. Run the test. Does it pass? Iteration is fast, cheap, and continuous. This is what makes agentic coding loops possible in software — the agent can try, fail, observe the error, and adjust in real time.

In chip design, the equivalent feedback loop takes hours or days. A simulation run to verify RTL behavior might run overnight. A synthesis pass to check timing might take half a day. You cannot build a fast agentic iteration loop on top of a slow verification pipeline. As highlighted at DVCon 2025, verification already consumes approximately 55% of ASIC/IC project costs — the feedback loop bottleneck is not a new problem, and AI doesn’t dissolve it.

3. The Correctness Bar Problem

In software, “good enough to ship” is a legitimate standard. You can iterate after release. In chip design, the correctness bar is absolute. A timing violation that escapes to silicon costs millions of dollars and months of re-spin time. An AI-generated RTL block that is “generally correct” is not acceptable. It must be provably correct under every operating condition, corner, and voltage — a bar that current models cannot reliably meet for complex designs.

4. The Proprietary Toolchain Problem

Software development tools are widely documented, many are open source, and AI models have been trained on tutorials and community discussions about them at scale. The EDA toolchain — Cadence, Synopsys, Siemens — is almost entirely proprietary. Tool behavior, constraint formats, SDC syntax, PDK rules: none of this exists in AI training data at meaningful scale. Until EDA vendors expose their tools through standardized interfaces — the Model Context Protocol is one emerging path — this knowledge gap will persist.

These four factors compound. Small training corpus means weaker base models. Slow feedback loops mean you can’t compensate with fast iteration. High correctness bar means you can’t ship “good enough.” Proprietary toolchains mean models can’t learn from real tool interactions.

Figure 3: The four structural reasons software AI runs ahead

Part 4: What Chip Design Needs to Do

The Path Forward — And Why It’s Not Hopeless

None of this means chip design AI is doomed to permanent lag. The structural problems are real, but they’re not unsolvable. They just require a different strategy than copying what worked in software.

1. Build the Knowledge Infrastructure First

The single highest-leverage investment chip design organizations can make right now is not deploying more AI tools — it’s making their existing knowledge accessible to AI. Years of design reviews, post-mortems, simulation logs, constraint files, and engineering decisions are sitting in formats that AI cannot reason over. That knowledge exists. It’s locked in PDFs, email threads, and proprietary tool outputs.

One team in our network reduced new engineer onboarding time significantly — simply by making years of post-mortems and design reviews searchable by AI. The knowledge existed. It just wasn’t accessible. Building the infrastructure to ingest, structure, and retrieve that knowledge — what is sometimes called a “design telemetry” layer — is the precondition for everything else. Without it, AI tools are operating without memory. With it, the domain-specific knowledge that makes chip design hard for generic AI becomes a competitive advantage.

2. Invest in the Feedback Loop

The slow verification pipeline is the bottleneck that prevents agentic AI from working in chip design the way it works in software. This is being attacked from multiple directions — faster formal verification, ML-based timing prediction, faster emulation platforms. The industry needs to treat accelerating the feedback loop as a first-class infrastructure investment. Every order-of-magnitude reduction in verification time is a direct multiplier on what AI can accomplish.

3. Pursue Circuit Foundation Models — But Patiently

The research is real. Models such as CircuitFusion (ICLR 2025) and NetTAG (DAC 2025) are early demonstrations of multimodal circuit models that reason across RTL, netlists, and layout simultaneously. This is the foundation model moment for chip design. But it will arrive on a longer timeline than software foundation models did. The right posture: build the knowledge infrastructure now so it’s ready to plug in when foundation models mature.

4. Adopt a “Senior Engineer Leverage” Model

The mistake to avoid is trying to replicate software’s out-of-loop agentic model before the infrastructure exists to support it. The appropriate model today is human-in-the-loop by design — not as a compromise, but as the right architecture for the current moment.

A senior engineer who supervises AI-generated first drafts — grounded in the company’s own design history — across two or three times their previous throughput is not a failure of AI ambition. It is a commercially sound and technically honest deployment of what AI can actually deliver today. The teams that figure this out now won’t just be more productive. They’ll be training on better data, building faster feedback loops, and compounding advantages that a late mover in 2027 simply cannot buy.

Watch the Toolchain Standardization Closely

The emerging Model Context Protocol (MCP) represents a potential inflection point for EDA. If major vendors ship MCP servers that expose tool data in standardized, AI-readable formats, the proprietary toolchain problem starts to dissolve. The organizations that build AI workflows on top of that emerging standard — rather than waiting for it to fully mature — will have a significant head start.

Figure 4: The strategic roadmap — from hype to hardware reality

Closing Thought

The hype cycle exists for a reason. It is a reliable description of how human expectations interact with emerging technology — overshoot, correction, and gradual convergence on reality. Chip design AI is not behind because the engineers are less capable or the ambition is smaller. It’s behind because the domain is genuinely harder.

That hardness is also a moat. The organizations that do the structural work — building knowledge infrastructure, investing in feedback loops, deploying AI with appropriate human oversight — will compound that work into durable advantages that late movers cannot easily replicate.

The bottleneck doesn’t disappear with AI. It moves. The question is whether you’re positioned on the right side of where it moves to.

---